1. Field of the Invention
This invention is related to a basic cell for gate arrays, and more particularly to a structure of a basic cell for gate arrays that are used in complementary metal-oxide silicon (CMOS) designs.
2. Description of Related Art
Because of shorter turn-around time, gate arrays are popularly used in the implementation of very-large-scale-integrated (VLSI) designs. In the manufacturing of an integrated circuit using gate arrays, an array of cells is pre-fabricated on the stage wafers prior to formation of metallization levels. After any circuit design is finished, the task to complete the remainder process is only to program the metal layers. The turn around time of gate array designs is obviously shorter than that for fully custom or standard cell designs. However, the fixed cell structure leads to some design limitations and difficulties.
FIG. 1 is a diagram of a conventional cell for gate arrays. The cell consists of four active areas 110, 120, 130, and 140. Active areas 110 and 120 are for P-type transistors, and the active areas 130 and 140 are for N-type transistors. Each one of the active areas is composed of two transistors. For example, there are two P-type transistors 111A and 111B in the active area 110. There are two P-type transistors 111C and 111D in the active area 120. There are two N-type transistors 112A and 112B in the active area 130. There are two N-type transistors 112C and 112D in the active area 140. Each one of the transistors 111A-111D and 112A-112D has a source terminal, gate terminal, and drain terminal. Two transistors in the same active area share a common source or drain terminal. All rectangles in the diagram, such as those designed by reference number 101, represent possible grids for signal interconnection in this embodiment.
A substrate tap area is arranged between active areas. For example, substrate tap areas 121 and 122 in FIG. 1 are located between active areas 110 and 120, and 130 and 140 respectively. There are multiple substrate taps in the substrate tap areas 121 and 122, for example, substrate contacts 131 and 132. These substrate tap areas 121 and 122 are respectively used to provide a voltage reference to transistors 111A-111D and 112A-121D. For this purpose, the substrate contacts 131 and 132 are connected to an appropriate power bus.
Most traditional gate array cells, for example, gate array cell 100 in FIG. 1, are often used to form a 2-input NAND circuit. Each NAND circuit has four transistors, including two P-type transistors and two N-type transistors. All of the transistors in the gate arrays are of the same, which offers less design flexibility. Most designs need the effect of different-sized transistors to satisfy driveability concerns. When a transistor which must have more driving capacity is necessary to satisfy design requirement, several transistors are connected in parallel to be used for the purpose of increasing driving capability. This will result in the consumption of more silicon area, just to use transistors of the same size.
Moreover, the current flow produced by an N-type transistor is lager than that produced by a P-type transistor. That is, while driving a circuit by a P-type and an N-type transistors with the same size, the time to pull up a voltage by the P-type transistor is slower than the time to pull down the same voltage by the N-type one. This requires that the size of P-type transistors is larger than that of N-type ones to balance pull-up and pull-down time.
Furthermore, all of the aligned P-type and N-type transistors in the cell, such as transistor 111A and transistor 112A in FIG. 1, are disconnected. Most transistors used in the CMOS designs are in pairs, and each pair consists of a P-type and an N-type transistor. Since the gate signals of transistors in each pair usually share the same electrical node, the prior art requires two contacts and a short metal wire in order to form the pair. This increases routing complexity in the cell and will reduce routing resource during chip implementation stage. It also results in more silicon consumption in the chip.
In addition, the substrate tap areas 121 and 122 are located between active areas 110 and 120, 130 and 140 respectively, which makes the body of gate arrays wider because the substrate tap areas 121 and 122 occupy a column of gate arrays in the chip. We have to take the arrangement of substrate tap areas in gate arrays into consideration when we try to avoid area consumption.
Certainly, less design limitations and less silicon consumption are the two major objectives in gate array designs. This invention provides more design flexibility to meet requirements of different designs. It also takes the routing complexity into consideration. This invention accommodates an optimal layout density with minimal waste area and offers an efficient implementation for different CMOS designs.